Dr. Alpana Agarwal

Dr. Alpana Agarwal

Designation:

Professor and Head

Specialization:

VLSI Design, Microelectronics

Email:

alpana@thapar.edu

Contact No.: 9417397370, 9115608836

Education:

  • Ph.D. Topic –“Synthesis of Analog IC Building Blocks” under the supervision of Dr. Chandra Shekhar, CEERI Pilani.
  • M.Tech. (Solid State Materials), GATE Scholarship recipient, Indian Institute of Technology, New Delhi
  • M.Sc. (Physics), Indian Institute of Technology, New Delhi

Experience

Academic (~27 years)

  • Associate Professor at Thapar Institute of Engineering & Technology, Patiala from January 1, 2006 to present.
  • Assistant Professor at Thapar Institute of Engineering & Technology, Patiala from August 1, 1996 to December 31, 2005 .
  • Birla Institute of Technology and Science, Pilani, Adjunct Faculty, 1990 – 1996.

Research (~29 years)

  • Central Electronics Engineering Research Institute, Pilani, Scientist - B, March 25, 1988 – March 24, 1992.
  • Central Electronics Engineering Research Institute, Pilani, Scientist - C , March 25, 19 92 – July 30, 199 6.
  • Thapar Institute of Engineering & Technology, Patiala Since August 1, 1996.

Sponsored Research Projects:

  • Completed/Ongoing 10 projects worth more than four (4) Crores from DoE/DIT/ DeitY, DST.
  • Worked on several projects at CEERI Pilani.
  • SMDP Chips to System Design, MeitY sponsored, Rs. 166 Lakhs , ( Consortium Budget 99.97 Crores ) 2 015 - 2020. ( Chief Investigator ) Ongoing
  • Low - Complexity Power - Efficient Reconfigurable Implementation of Fractional Order Filters for Weak ECG Nonstationary Biomedical Signal Processing Applications , DST SERB Sponsored, Rs. 53.95 Lakhs , 2016 – 19. (Co - PI ) Ongoing.
  • Special Man power Development Program for VLSI Design and Related Software (Phase – I), DOE sponsored, Rs. 75 Lakhs , 1998 – 2005. (Coordinator)
  • Special Man power Development Program for VLSI Design and Related Software (Phase – I), DOE sponsored, Rs. 75 Lakhs , 1998 – 2005. (Coordinator)

Major Publications:

  • Anil Singh and Alpana Agarwal , "Charge pump - based MOSFET - only 1.5 - bit pipelined ADC stage in digital CMOS technology", International Journal of Electronics, Vo. 103, No.10, pp. 1713 - 1725, 2016 (IF 0.729)
  • Anil Singh and Alpana Agarwal , "Digita l background calibration of charge pump based pipelined ADC", International Journal of Electronics, Vo l . 103, No.11, pp. 1941 - 1953, 2016 (IF 0.729)
  • Anil Singh and Alpana Agarwal , "Power and Area Efficient Pipelined ADC Stage in Digital CMOS Technology", IETE Technical Review, Vol. 34, No.1, pp. 66 - 74 , 2016 (IF 1.330)
  • Anil Singh, Ayushi Goel, and Alpana Agarwal , "A Digital - Based Low - Power Fully Differential Comparator", Journal of Circuits, Systems, and Computers, Vol. 26, pp. 1750002 - 14, 2017 , (IF 0.47 )
  • Anil Singh, Veena Rawat and Alpana Agarwal , "A Low Power 10 - bit 100 - MS/s Pipelined ADC in Digital CMOS technology", accepted for publication in IET Circuits, Devices & System, 2017 ( 1.092 )

International Conferences

  • Ajay Kumar and Alpana Agarwal , Research Issues Related to Cryptography Algorithms and Key Generation for Smart Grid: A Survey, 7 th International IEEE India International Conference on Power Electronics (IICPE – 2016), November 17 – 19, 2016.
  • Mansi Sharma and Alpana Agarwal , Survey on Authenticat ion and Encryption Techniques for Smart Grid Communication, 7 th International IEEE India International Conference on Power Electronics (IICPE – 2016), November 17 – 19, 2016.
  • Manu Bansal and Alpana Agarwal , Genetic Algorithm for Ordering and Reduction of B DDs for MIMO Circuits, The Third International Conference on Innovative Computing Technology London, UK, August 29 - 31, 2013
  • Madhusoodan Agarwal & Alpana Agarwal , A Combined CMOS Reference Circuit with Supply and Temperature Compensation, 17th International Symposium on VLSI Design and Test (VDAT2013) , July 28 – 30, 2013 .
  • Alpana Agarwal and Chandra Shekhar, Synthesis of Analog IC Building Blocks, IEEE Annual Symposium on VLSI (ISVLSI), Chennai, India July 4 - 6, 2011 .
  • Alpana Agarwal , A Voltage con trolled CMOS VGA with 40 dB Dynamic ra nge for MEMS Applications, Symposium H: MEMS Te chnology and Devices in Interna tional Conference on Materials for Advanced Technologie s 2007, July 1 - 6, 2007, Singa pore.
  • Varun Jindal and Alpana Agarwal , Carry Circuitr y for LUT - Based FPGA, Proceedings of the 17th International Conference on VLSI Design 2004 and ICES - 3, Jan. 7 - 9, 2004, Mumbai.

Other Publications

  • 27 in Peer reviewed International and nation al journals and conferences.
  • Reviewer in IEEE, Elsevier, Francis and Taylor, Springer journals.

Patent Filed

  • • Anil Singh and Alpana Agarwal , "Fully differential clocked comparator for pipelined analog - to - digital converter", filed Indian patent with Acknowl edge ment no. TEMP/E - 1/8400/2016 - DEL, Mar. 2016.

Thesis Guided

  • Guided 70 ME/M.Tech thesis
  • Guided 1 PhD student
  • Ongoing 5 PhD student guidance

Foreign Visits

  • Deputed to Trinity College, Dublin from Oct. 5 – Nov. 1, 2015 for learning international academic practices.
  • Visited Singapore and Australia for conference presentations

Expert Talks

  • Delivered more than 25 Expert/Invited talks at IIT Delhi, NIT Kurukshetra, MNIT Jaipur, NIT Jalandhar, NIT Hamirpur, PEC Chandigarh, USIC and Electronics Department – Kurukshetra University, BITS Pilani, CEERI Pilani, Chitkara University, MITS Lakshmangarh, MM University,
  • Delivered Invited Talks at about 10 conferences and workshops.

Short Term Courses/Workshops/Conferences Organized: 15

Short Term Courses/Workshops/Conferences Attended: More than 50

Course Material Developed

  • VLSI Design Concepts, AICTE, 2002
  • Digital Electronic Circuits, DDE, Thapar Institute of Engineering & Technology, 2006.
  • Electronic Devices and Circuits, DDE, Thapar Institute of Engineering & Technology, 2006.

Honours and Awards

  • My PhD thesis was chosen as one of ten best intern ational thesis in the domain of VLSI by IEEE /ISVLSI Community and was invited to present my work in ISVLSI 2011.
  • Best Thesis supervisor in PI category under the aegis of SMDP - VLSI (Phase – II) project. Student Award – Rs 1 0,000/ - , Supervisor Award – Rs. 15,000/ - and University Award – Rs. 1,50,000/ - (Ministry of Electronics and Information Technology). 2006
  • INSA Vising Scientist awarded during 2004 – 05.
  • Recipient of Cash awards under Performance Incentive Scheme of Thapar Institute of Engineering & Technology almost every year since 2007.
  • MHRD GATE Fellowship 1986 - 1987.
  • MD University Merit Award for standing 8 th . College award for standing 1 st .

Membership of Professional Organizations

  • Life Member, Institution of Electronics and Telecommunication Engineers (IETE)
  • Life Member, Semiconductor Society of India (SSI)
  • Life Member, Indian Physics Association (IPA)
  • Life Member, Metrology Society of India (MSI)
  • Member, VLSI Society of India (VSI)

Major Administrative Responsibilities

  • Head, Electronics and Communication Engineering Department, Thapar Institute of Engineering & Technology (Jan. 2017 onwards)
  • Presiding Officer, Internal Complaints Committee ( Jan 2014 – March 2017 )
  • UG Incharge 2002 - 04, 2012 - 2014, (2015 – 2016 )
  • PG Coordinator (2008 – 2012)
  • Laboratory Incharge, VLSI Desig n Lab, (2002 – 2015)
  • Laboratory Incharge, VLSI Chips to Systems (2015 – present)
  • Member, DPPC (2014 – Present)
  • Member, DAAC , BOS of ECED (Several occasions, Present)
  • Member, DAAC BE(Mechatronics) (2012 - Present)
  • Chief Student Counselor, Student Counseling Cell (April 2002 – 2013).
  • Departmental Student Counselor (1997 – 2002).
  • Member of Senate for 1997, 2000, 2004, 2007, 2008 - 09 , 2017 .
  • President, Environment Society (1997 – 2010)

Other Academic / Co-curricular / extra curricular activities

  • CAPSL Foundatio n Program: ‘New - Directions’ in Teaching & Learning - Special Purpose Certificat e in Academic Practice (SPCert) by Trinity College, Dublin, Ireland.
  • Developed ‘VLSI Design’ Laboratory.
  • Developed Laboratory manuals for ‘Microprocessors’, Digital Electronics’ , ‘Digital VLSI Design’, ‘Analog IC Design’, Hardware Deion Languages’.
  • Member UG and PG Curriculum Design Committee
  • Member UG and PG admission Committee
  • Member Board of Governors, 2008 - 09.
  • Member Staff Affairs Committee 2008 – 09.
  • Member BOS at va rious universities
  • Examined PhD, ME/MTech. Thesis evaluations at various universities .