Dr. Rajneesh Sharma

Dr. Rajneesh Sharma

Designation:

Assistant Professor

Specialization:

Analytical modeling of Nanoscale transistors, Low leakage device design, Underlap strained SOI device design and optimization, Device-circuit co-design for low power VLSI applications

Email:

rajneesh.sharma@thapar.edu

Contact Number

+91-8219499469

Assistant Professor

rajneesh.sharma@thapar.edu

Biography

Dr. Rajneesh Sharma is working with Electronics and Communication Department, Thapar Institute of Engineering and Technology, Patiala since 2018. He has total five years of teaching experience in government as well as private institutions. . His research interests include Nanoscale Device Design and Modeling, SOI based planar and non-planar FETs for low power VLSI design, Novel MOSFETs for low leakage current.

Education

  • Ph.D. in Electronics and Communication Department from NIT Hamirpur (HP).
  • M. Tech in VLSI Design Automation and Techniques from NIT Hamirpur (HP).
  • B.Tech. in Electronics and Communication Engineering from P.T.U. Jalandhar.

Experience: Total Teaching Experience 4 years 8 month

  • July 2010 – November 2012: Assistant Professor, Lovely Professional University, Phagwara, Jalandhar.
  • October 2016 – August 2017: Lecturer, NIT Hamirpur (HP).
  • August 2017 – June 2018: Assistant Professor, Dr. B. R. Ambedkar NIT Jalandhar (Punjab).

Teaching Interests:

  • Semiconductor Device Physics
  • CMOS VLSI Design
  • Digital VLSI Design using Verilog/VHDL
  • Digital Electronics
  • Linear Integrated Circuits

Research Interest:

  • Nanoscale device design and modeling
  • Novel MOSFET structures for low power application
  • SOI based design for IoTs

Publications:

Journals

  1. Rajneesh Sharma and Ashwani K. Rana, “Scalability Projection of Underlap Fully Depleted Strained Ultra Thin Body Silicon-on-Insulator MOSFETs Using Quantum Potential Simulations,” Journal of Nanoelectronics and Optoelectronics, vol. 11, no. 4, pp. 472-476, 2016. (SCI/SCIE Indexed IF = 1.096). li>
  2. Rajneesh Sharma and Ashwani K. Rana, “Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET,” International Journal of Electronics, vol. 104, no. 2, pp. 286-296, 2016. (SCI/SCIE Indexed IF = 0.939).
  3. Rajneesh Sharma, Rituraj Singh Rathore and Ashwani K. Rana, “Nanoscale Static Random-Access-Memory Design Using Strained Underlap Ultra Thin Silicon on Insulator MOSFET for Improved Performance,” Journal of Nanoelectronics and Optoelectronics, vol. 12, no. 4 pp. 359-364, 2017. (SCI/SCIE Indexed IF = 1.096).
  4. Rajneesh Sharma, Rituraj Singh Rathore and Ashwani K. Rana, "Impact of high-k spacer on device performance of nanoscale underlap fully depleted SOI MOSFET" Journal of Circuits, Systems, and Computers, vol. 27, no. 4, pp. 1850063 (13 pages), 2018. (SCI/SCIE Indexed IF = 0.595).
  5. R. S. Rathore, Rajneesh Sharma, and A. K. Rana, “Line edge roughness induced threshold voltage variability in nano-scale FinFETs,” Superlattices and Microstructures, vol. 103, pp. 304-313, 2017. (SCI/SCIE Indexed IF = 2.099) .
  6. R. S. Rathore, Rajneesh Sharma, and A. K. Rana, “Threshold voltage variability induced by spacer and resist defined patterning techniques in nano-scale FinFETs,” Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 16, no. 1, pp. 013503, 2017. (SCI/SCIE Indexed IF = 1.299).

International Conferences

  1. Rajneesh Sharma and Shekhar Verma, “Comparative Analysis of Static and Dynamic CMOS Logic Design,” IEEE International Conference on Advanced Computing and Communication Technologies, APIIT Panipat, Haryana India, pp 231-234, 5 November 2011.
  2. Rajneesh Sharma and Ashwani K. Rana, “Strained Si: Opportunities and Challenges inNanoscale MOSFET” IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS-2015), Jadavpur University, Kolkata India, 9-11 July, 2015.
  3. Rajneesh Sharma, Rituiraj Singh Rathore and Ashwani K. Rana, “A 6T SRAM cell design using nanoscale strained underlap UTSOI MOSFET for improved performance,” 10th International Conference on Advanced Computing & Communication Technologies (10-ICACCT 2016), APPIT SD, Panipat, Haryana, India, 18-20 November, 2016.
  4. R. S. Rathore, Rajneesh Sharma, and A. K. Rana, “Impact of work function fluctuations on threshold voltage variability in a Nano-scale FinFETs,” IEEE International Symposium on Nano electronic and Information System (iNIS 2016), Gwalior, M.P, India, Dec 2016.
  5. R. S. Rathore, Rajneesh Sharma, and A. K. Rana, “Threshold voltage variability induced by statistical parameters fluctuations in nanoscale bulk and SOI FinFETs,” 4th International conference on ‘Signal Processing, Computing and Control (ISPCC-2017), JUIT Solan, H.P., India, 21-23 September, 2017.

National Conferences

  1. Rajneesh Sharma and Rajeevan Chandel, “Performance Analysis of Static and Dynamic CMOS Logics” National Conference on Recent Advances in Electrical & Electronics Engineering, National Institute of Technology Hamirpur, Himachal Pradesh India, 23 December 2009.